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<div class="title">Hardware Requirements </div>  </div>
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<div class="textblock"><p>The following section lists the hardware requirements for RTX v5 on the various supported target processors:</p>
<h1><a class="anchor" id="tpProcessor"></a>
Processor Requirements</h1>
<p>RTX assumes a fully functionable processor and uses the following hardware features. It does not implement any confidence test for processor validation which should be provided by an user-supplied software test library.</p>
<h2><a class="anchor" id="tpCortexM0_M0P_M23"></a>
Cortex-M0/M0+/M23 target processor</h2>
<table class="doxtable">
<tr>
<th align="left">Hardware Requirement </th><th align="left">Description  </th></tr>
<tr>
<td align="left">SysTick timer </td><td align="left">The SysTick timer generates the kernel tick interrupts and the interface is implemented in os_systick.c using the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> </td></tr>
<tr>
<td align="left">Exception Handler </td><td align="left">RTX implements exception handlers for SVC, PendSV, and SysTick interrupt </td></tr>
<tr>
<td align="left">Core Registers </td><td align="left">The processor status is read using the following core registers: CONTROL, IPSR, PRIMASK </td></tr>
<tr>
<td align="left">System Control Block (SBC) </td><td align="left">To control and setup the processor exceptions including PendSV and SVC </td></tr>
<tr>
<td align="left">Interrupt Control </td><td align="left">The CMSIS-Core functions __disable_irq and __enable_irq to control the interrupt system via the CPSR core register. </td></tr>
</table>
<p>The RTX implements interfaces to the processor hardware in following files:</p>
<ul>
<li><b>irq_armv6m.s</b> defines exception handlers for Cortex-M0/M0+</li>
<li><b>irq_armv8mbl.s</b> defines exception handlers for Cortex-M23</li>
<li><b>rtx_core_cm.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.</li>
<li><b>os_tick.h</b> is the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> that defines the interface functions to the SysTick timer.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd><ul>
<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used by RTX to configure the SysTick timer.</li>
</ul>
</dd></dl>
<h2><a class="anchor" id="tpCortexM3_M4_M7_M33_M35P"></a>
Cortex-M3/M4/M7/M33/M35P target processor</h2>
<p>RTX assumes a fully function-able processor and uses the following hardware features:</p>
<table class="doxtable">
<tr>
<th align="left">Hardware Item </th><th align="left">Requirement Description  </th></tr>
<tr>
<td align="left">SysTick timer </td><td align="left">The <b>SysTick</b> timer shall be available in the processor. </td></tr>
<tr>
<td align="left">System Exceptions </td><td align="left">The RTX requires <b>SVC</b>, <b>PendSV</b>, and <b>SysTick</b> exceptions and implements corresponding exception handlers. </td></tr>
<tr>
<td align="left">Core Registers </td><td align="left">The RTX uses <b>CONTROL</b>, <b>IPSR</b> , <b>PRIMASK</b> and <b>BASEPRI</b> core registers for reading processor status. </td></tr>
<tr>
<td align="left">System Control Block (SCB) </td><td align="left">The RTX uses <b>SCB</b> registers to control and setup the processor system exceptions including PendSV and SVC. </td></tr>
<tr>
<td align="left">NVIC Interface </td><td align="left">CMSIS-Core function <b>NVIC_GetPriorityGrouping</b> is used by the RTX to setup interrupt priorities. </td></tr>
<tr>
<td align="left">LDREX, STREX instructions </td><td align="left">Exclusive access instructions <b>LDREX</b> and <b>STREX</b> are used to implement atomic execution without disabling interrupts. </td></tr>
</table>
<p>The interface files to the processor hardware are:</p>
<ul>
<li><b>irq_armv7m.s</b> defines exception handlers for Cortex-M3 and Cortex-M4/M7.</li>
<li><b>irq_armv8mml.s</b> defines exception handlers for Cortex-M33/M35P</li>
<li><b>rtx_core_cm.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.</li>
<li><b>os_tick.h</b> is the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> that defines the interface functions to the SysTick timer.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd><ul>
<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used by RTX to configure the SysTick timer.</li>
</ul>
</dd></dl>
<h2><a class="anchor" id="tpCortexA5_A7_A9"></a>
Cortex-A5/A7/A9 target processor</h2>
<table class="doxtable">
<tr>
<th align="left">Hardware Requirement </th><th align="left">Description  </th></tr>
<tr>
<td align="left">Timer Peripheral </td><td align="left">An arbitrary timer peripheral generates the kernel tick interrupts. The interfaces for Cortex-A Generic Timer and Private Timer are implemented in os_tick_gtim.c and os_tick_ptim.c using the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> </td></tr>
<tr>
<td align="left">Exception Handler </td><td align="left">RTX implements exception handlers for SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction interrupt. </td></tr>
<tr>
<td align="left">Core Registers </td><td align="left">The processor status is read using the following core registers: CPSR, CPACR and FPSCR. </td></tr>
<tr>
<td align="left">LDREX, STREX instruction </td><td align="left">Atomic execution avoids the requirement to disable interrupts and is implemented via exclusive access instructions. </td></tr>
<tr>
<td align="left">Interrupt Controller </td><td align="left">An interrupt controller interface is required to setup and control Timer Peripheral interrupt. The interface for Arm GIC (Generic Interrupt Controller) is implemented in irq_ctrl_gic.c using the <a href="../../Core_A/html/group__irq__ctrl__gr.html" class="el">IRQ Controller API</a>. </td></tr>
</table>
<p>The interface files to the processor hardware are:</p>
<ul>
<li><b>irq_armv7a.s</b> defines SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction exception handlers.</li>
<li><b>rtx_core_ca.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.</li>
<li><b>os_tick.h</b> is the <a class="el" href="group__CMSIS__RTOS__TickAPI.html">OS Tick API</a> that defines the interface functions to the timer peripheral.</li>
<li><b>irq_ctrl.h</b> is the <a href="../../Core_A/html/group__irq__ctrl__gr.html" class="el">IRQ Controller API</a> that defines the interface functions to the interrupt controller.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd><ul>
<li>The CMSIS-Core variable <code>SystemCoreClock</code> is used by RTX to configure the timer peripheral.</li>
</ul>
</dd></dl>
<h1><a class="anchor" id="rMemory"></a>
Memory Requirements</h1>
<p>RTX requires RAM memory that is accessible with contiguous linear addressing. When memory is split across multiple memory banks, some systems do not accept multiple load or store operations on this memory blocks.</p>
<p>RTX does not implement any confidence test for memory validation. This should be implemented by an user-supplied software test library. </p>
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